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As ST_ACEPACK-2-CIB, https://www.infineon.com/dgdl/Infineon-FP50R06W2E3-DS-v02_02-EN.pdf?fileId=db3a30431b3e89eb011b455c99987d24 24-lead TH, Package W, https://www.littelfuse.com/~/media/electronics/datasheets/power_semiconductors/littelfuse_power_semiconductor_igbt_module_mg1275w_xn2mm_datasheet.pdf.pdf 35-lead TH, Package W, https://www.littelfuse.com/~/media/electronics/datasheets/power_semiconductors/littelfuse_power_semiconductor_igbt_module_mg1275w_xn2mm_datasheet.pdf.pdf 35-lead TH, EasyPIM 2B, same as Infineon_AG-ECONO2, https://www.littelfuse.com/~/media/electronics/datasheets/power_semiconductors/littelfuse_power_semiconductor_igbt_module_mg1225h_xn2mm_datasheet.pdf.pdf 24-lead TH, Package H, same as above if not a standard font on any OS; get it here. Might be able to add picture 9f9f6acf76 Add notes about wiring SW15 cross-board Add design rules for jlcpcb Latest commits for branch schematic Merge pull request synth_mages/MK_VCO#7 Updates from real TL0x4s Merge pull request 'Finish schematic, add PDF' (#2) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file c4e1c30b9b Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace order number text Things best left to external modules: CV-controlled CV offset module - add a switch to disable clock (pause). SPST switch per step, to set clock rate (if onboard clock is used // 11 SPDT switches: // 1 rotary switch - 9.5mm, +5mm extra space available mini toggle pushbuttons: ample space above 11.75mm (existing 1p12t rotaries, use 11.25mm holes to PCB edge 8.2mm, see https://disti-assets.s3.amazonaws.com/tonar/files/datasheets/16730.pdf 37-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.54mm pin-PCB-offset 9.4mm 9-pin D-Sub connector horizontal angled 90deg THT female pitch 2.77x2.84mm pin-PCB-offset.

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