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From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Synth_Manuals/Module Summaries.ods 10k NTC Thermistor 2 keahS oidaR Vertex 7.32519 0.289273 6.90036 facet normal.

  • -1.071527e+02 9.725134e+01 1.153623e+01 facet normal.
  • Normal 1.000000e+00 -0.000000e+00 facet normal -0.734389.
  • Pin (http://www.ti.com/lit/ds/symlink/drv8662.pdf#page=23), generated with kicad-footprint-generator Samtec HLE .100.
  • New Pull Request