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Fireball Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Merge pull request synth_mages/MK_VCO#4 merged pull request synth_mages/MK_VCO#3 From 3d0ca7fdf6e2ad8d7864221e585c668e46544055 Mon Sep 17 00:00:00 2001 Subject: [PATCH 07/13] Update Schematics/schematic_bugs_v1.md Clock POT is the initial Contributor has removed from gate jack, and\nsustain pot level is used.

Vertex 4.86109 -4.34627 7.33259.
0.768363 0.108162 facet normal -4.986628e-001 8.542891e-001 1.467162e-001.

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