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BackTue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: merged pull request 'Fix rail clearance issues, make all power traces large Add ground fills, fix some clearance issues, add PCB.
- 0.920082 -0.0906197 0.381101 vertex -0.373379 -10.0771 2.58057 vertex.
- 0.0735183 facet normal -0.343403.
- Up (PowerSO-20) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf.