synth_tools

Back

Http://www.ti.com/lit/ds/symlink/ts3a24159.pdf Texas Instruments, NDQ, 5 pin (https://www.ti.com/lit/ml/mmsf022/mmsf022.pdf TO-PMOD-11 11-pin switching regulator package, http://www.ti.com/lit/ml/mmsf025/mmsf025.pdf Vishay PowerPAK 1212-8 Dual (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72598/72598.pdf PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf Vishay PowerPAK 1212-8 Single Zetex, SMD, 8 pin DIP socket A-001 1 14 pin DIP socket | | | | C1, C11, C12 | 1 | ICM7555xP | CMOS General Purpose Timer, 555 compatible, PDIP-8 | | | | | Tayda | A-3486 or A-3487\*\*\* | | | R9, R11, R13 | 3 | 2_pin_Molex_connector | 2 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= 969311f00cbb6d6ece9a25b5fb1d4e2884e468c0 Assorted updates From 4675f71e05fc19d3608ee6e5061bbe79ae432fb7 Mon Sep 17 00:00:00 2001 Subject: [PATCH] achewood, gwss fix, fix for when invisible bread has no bread achewood, gwss fix, fix for when invisiblebread has no bread function rel2abs($rel, $base $path = preg_replace('#/[^/]*$#', '', $path); if ($rel[0] == '/') { $path = ''; } main synth_tools/PSU/psu.diy 1077 lines From 215821e48128fa87907c6added840580ad4c06ac Mon Sep 17 00:00:00 2001 Subject: [PATCH 10/18] More tweaks after pro review }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", "specctra_dsn": "", "step": "", "vrml": "" }, "page_layout_descr_file": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, "drawing": { More tweaks after pro review More tweaks after pro review }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", "specctra_dsn": "", "step": "", "vrml": "" }, "schematic": { "annotate_start_num": 0, "drawing": { More tweaks after pro review } ], "meta": { "version": 3 }, "net_colors": null, "netclass_assignments": null, updates to rev 2 beta by adding.

New Pull Request

Labels Milestones