3
1
Back

File Images/PXL_20210831_004139245.jpg 054c37512a Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/POLYMORPH.png' 9bb3093b2bc14210884f0107e7a2898b2161266b Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/HOLD PORTAL.png' Delete '3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/SPIDER CLIMB.png' 4049c4aafe Delete '3D Printing/Panels/image.png' 935360b933 Delete '3D Printing/Panels/MAGIC MISSILE VCF.png and /dev/null differ From e825437e5db64d4ef13181f883b9fe719cf4c2a1 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add design rules for jlcpcb Add design rules for jlcpcb 9360e76802 Add design rules for jlcpcb Add design rules for jlcpcb 9360e76802 Add design rules for jlcpcb 4ee6887723 Add some perfboard sections, power headers, teardrops checkpoint before getting really weird with WireIt A couple more GND-stitch vias eb8580ef62 Undo converting GND to GND_JMP and fix everything that broke 3583986e89 Finished PCB, passes.

New Pull Request