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Back20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Minor layout tweaks Minor layout tweaks Minor layout tweaks Finish schematic, add PDF | J6 | 1 | B10k | \*\*Potentiometer, 9 mm pots, you're on your own! * The first two groups should be 10 nF. Putting everything together is a ceramic 104 power cap like C5, C6, C8, C9 Schottky Barrier Rectifier Diode, DO-41"/>