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BackPrecadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/Panel/precadsr_panel_al/sym-lib-table Normal file Unescape Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod Normal.
- SOT-93, see https://www.vishay.com/docs/95214/fto218.pdf TO-218-2.
- Gitea runs anywhere Go can compile for: Windows.
- , length*diameter=3.2*2.6mm^2, , http://www.diodes.com/_files/packages/T-1.pdf Diode T-1.
- Updates Checkpoint after re-centering.