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Ird, lf, sh, fn, rn [ ord*cos(lf0), ord*sin(lf0), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ord*cos(lf1), ord*sin(lf1), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: merged pull request 'pcb_finalization' (#1) from bugfix/10hp into main 26b0f01955 Fix for component clearance, panel thickness from printer realities bugfix/10hp More layout updates created pull request synth_mages/MK_VCO#5 Merge pull request synth_mages/MK_VCO#3 From 3d0ca7fdf6e2ad8d7864221e585c668e46544055 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 ; FORMAT={-:-/ absolute / metric / decimal} Schematics/schematic_bugs_v1.txt Normal file Unescape 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_24.stl.

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