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BackSimulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: unplated through holes: merged pull request synth_mages/MK_VCO#5 Merge pull request 'pcb_finalization' (#1) from pcb_finalization into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/1 Merge pull request 'Put title box in PDF export Merge pull request 'pcb_finalization' (#1) from bugfix/10hp into main Merge pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/4 Put title box in PDF export' (#4) from schematic into main Merge pull request synth_mages/MK_VCO#3 created pull request.
- Https://neosid.de/import-data/product-pdf/neoFestind_Ms50.pdf Neosid Power Inductor WE-PDF Wuerth.
- Plasic small outline package; 18 leads.
- 5.735729e-001 2.554278e-003 8.191506e-001 vertex -5.112638e+000.
- -0.991507 -0.0942884 0.0895734 facet.