Labels Milestones
BackKiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Panels/title_test_22.stl
Examples
- Michael de Miranda
- 0.260353 -0.938727 0.22585 facet normal 9.734658e-001 2.288326e-001 0.000000e+000.
- MGJ2DxxxxxxSC, 19.5x9.8x12.5mm, 5.2kVDC Isolated, 1W, single.