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From 8e97a73397a03125f3bf5b9aa13372a2d7319ad0 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change transistor footprint to inline_wide, fix DRC ground plane created pull request synth_mages/MK_VCO#5 Add jlc constraints DRC; replace order number text Compare 19 commits » created pull request 'new_footprints' (#5) from new_footprints into main v1 Final tweaks, version submitted to JLCPCB on 20240124 Final tweaks, version submitted to JLCPCB on 20240124 63579cf959 Add notes about wiring SW15 cross-board 9360e76802 Add design rules for jlcpcb Add design.

Vertex -8.21035 3.40084 5.07603 facet.
Normal 0.000209061 0.115803 0.993272 facet normal -0.714669.
See https://standexelectronics.com/de/produkte/ms-reed-relais/ Standex Meder MS SIL reed.
9774020633 (https://katalog.we-online.com/em/datasheet/9774020633.pdf), generated with kicad-footprint-generator.

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