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Designed using KiCad: https://www.kicad.org/ # Format documentation: https://kicad.org/help/file-formats/ # Temporary files fp-info-cache # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Schematics/SynthMages.pretty/6.3mm_NPTH_MAXJLCPCB.kicad_mod Latest commits for file Panels/luther_triangle_10hp_rib_space_fixes.stl main MK_VCO/Panels/Font files/futura medium bt.ttf Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-NPTH.drl Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-NPTH.drl Normal file View File 3D Printing/Jigs/eurorack_test_jig_150mm.stl Executable file View File Hardware/PCB/precadsr/sym-lib-table Normal file Unescape Schematics/SynthMages.pretty/Jack_3.5mm_QingPu_WQP-PJ398SM_Vertical_CircularHoles_Socket_Centered.kicad_mod Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.sch Normal.

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