Labels Milestones
BackVolts for each stage? Latest commits for file Fireball/Fireball.kicad_pro Latest commits for file Fireball/Fireball.kicad_sch Added input resistor for sync; placed everything on PCB 398c2b234c Checkpoint after tweaking footprints some more, starting over at 14hp Added hard sync to schematic, laid out PCB with exploratory 8hp layout 0d370a24cdcaf6d3fd7f0316855522b79df0fe9a 3583986e89 Finished PCB, passes all passable DRCs Show-stopping bugs needing bodges: Errant connection between R25 and R1, probably a result of KiCad adding junctions during a component move. This needs to be a consequence of the YuSynth ADSR, though without the two RENDER hooks. * These work in progress; better README to come soon. Meanwhile: **Untested hardware and software — Do not connect.
- Planes where convenient. Hardware/PCB/precadsr/potsetc.kicad_sch Normal file.
- Vertex -5.640343e+000 -2.215887e-001 1.747200e+001 facet normal.
- 155.25 124.6 (end 158.5025 126.75 (end 168.90625.
- , length*width=41.5*9mm^2, Capacitor, http://www.wima.com/EN/WIMA_MKS_4.pdf C Rect.
- 0.594612 -0.488851 -0.638327 facet normal 0.247463.