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Back-2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone --recurse-submodules git@github.com:holmesrichards/precadsr.git git clone git@github.com:holmesrichards/precadsr.git git clone git@gitlab.com:rsholmes/precadsr.git git submodule update ``` ``` aoKicad/ao_symbols Kosmo_panel/Kosmo ``` and footprint libraries ``` aoKicad/ao_tht Kosmo_panel/Kosmo_panel. ``` From 5cacbfea2e523d618ea3bcbc0bca9c37eb36f10d Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix getting a bunch of wires backwards From 16055f0ae510d4466f2b156df715b3e97e4555d8 Mon Sep 17 00:00:00 2001 Subject: [PATCH] github url .../PCB/precadsr_Gerbers/precadsr-B_Cu.gbr | 4 | 100k | Resistor | | | | | | | | | | | C6, C7, C8, C9 | 4 812d609d12 More assembly notes 48c8a4e4f4 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/UNSEEN SERVANT.png PCB Notes.txt Notes from debugging Clock POT is too small for a single 0.5 mm² wires, basic insulation, conductor diameter 0.4mm, outer diameter 2.3mm, size source Multi-Contact FLEXI-E 0.75 (https://ec.staubli.com/AcroFiles/Catalogues/TM_Cab-Main-11014119_(en)_hi.pdf), bend radius 3 times outer diameter, generated with kicad-footprint-generator Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-126-02-xxx-DV-BE-LC, 26 Pins per row (https://www.molex.com/pdm_docs/sd/022057045_sd.pdf), generated with kicad-footprint-generator JST PHD series connector, B28B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator Molex MicroClasp Wire-to-Board System, 55932-0230, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py WSON-10 package 2x3mm body, pitch 0.5mm (http://www.analog.com/media/en/package-pcb-resources/package/56702234806764cp_24_3.pdf, http://www.analog.com/media/en/technical-documentation/data-sheets/ADL5801.pdf LFCSP VQ, 48 pin, exposed pad, thermal vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/ Infineon SO package.
- -0.877371 0.110936 facet normal -9.468313e-002 9.955075e-001 0.000000e+000.
- 6.982779e-002 vertex -1.978528e+000 -3.524848e+000 2.470218e+001.
- BSD: back surdo For this.