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Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: ============================================================= 77735c00cc3285131373f5cfc61b82eab5963d12 c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score caixa_sr1.png | Bin 0 -> 11930 bytes create mode 100644 Hardware/PCB/precadsr/ao_symbols.lib delete mode 100644 Panels/FireballSpellVertVerySmall.png create mode 100644 Fireball/Fireball.kicad_dru create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-F_Paste.gbr create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Jack_Hole.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/drill_report.rpt create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/3PDT-toggle-switch-1M-seriesx.kicad_mod create mode 100644.

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