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BackLTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be 531ebcae92ad8ad00635060e3583259ee13cc12b e49f4ab127dc081ee1c77dd21e80d128628a1152 5ff3077e8252367b7eceb0b21b0803904b695d42 Fix sr2 blue Fix sr2 blue Samurai formatting caixa bits caixa_sr1.png | Bin 0 -> 38764 bytes .../Font files/futura medium bt.ttf Normal file Unescape Schematics/SynthMages.pretty/Perfboard_2x12.kicad_mod Normal file Unescape "Name": "Top Silk Screen" "Name": "Top Solder Paste" "Name": "Bottom Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Solder Paste" "Name": "Top Solder Mask" "Name": "Bottom Solder Paste" "Name": "Bottom Silk Screen" Hardware/Panel/precadsr-panel/precadsr-panel-cache.lib Normal file Unescape // pots (all p160s): /* [Default values] */ // // this should.
- Vertex -2.186956e+000 6.678942e+000 9.983999e+000.
- -0.295599 0.346103 0.890412 facet normal -0.0168607 -0.828714.
- -0.338907 0.937991 facet normal 8.724472e-001.
- -0.284755 0.938725 0.194192 vertex -9.81063.
- 1x11 1.00mm single row style1 pin1 left.