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Back-0.0817037 -0.0823248 0.993251 vertex -5.77664 -4.28775 7.9152 facet normal 0.479685 -0.847874 0.225859 facet normal 0.766709 -0.634273 0.099275 vertex 7.28969 -6.84547 0 facet normal 0.622326 0.758285 0.194199 facet normal 0.575169 -0.528289 0.624573 facet normal -9.482393e-01 -5.548876e-03 3.175082e-01 facet normal 5.086343e-001 3.109915e-003 8.609771e-001 facet normal -1.489001e-15 -5.217420e-15 1.000000e+00 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ## GitHub repository * [https://github.com/holmesrichards/precadsr](https://github.com/holmesrichards/precadsr ## Submodules This repo uses submodules aoKicad and Kosmo_panel, which provide needed libaries for KiCad. To clone: schematic start, and some example modules Latest commits for file Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache # Autorouter files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes.
- Both GND) 6x Sockets, 2pin: .
- Unescape Hardware/PCB/precadsr/ao_tht.pretty/Molex_KK-254_AE-6410-02A_1x02_P2.54mm_Vertical.kicad_mod Normal file.