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Vs (10.54+1.52) mm if I'm reading it right. Latest commits for file Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files fp-info-cache # Netlist files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema) *.net # Autorouter files (exported from Eeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= f51b7b97734e404127fa5d5d263acbfd66f116e4 Bring in diylc.

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