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Back"Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Latest commits for file Examples/precadsr.pdf Binary files a/3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/MAGIC MOUTH.png main ENV/Envelope/Envelope.kicad_pro 333 lines LUTHERS_VCO.diy Executable file Unescape Hardware/PCB/precadsr/ao_tht.pretty/Molex_KK-254_AE-6410-02A_1x02_P2.54mm_Vertical.kicad_mod Normal file View File # For PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # Temporary files *.000 *.bak Initial version *.dsn *.ses */fp-info-cache c58f541d7e Upload files to '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/COLOR SPRAY.png' Delete '3D Printing/Panels/image.png' 6523065365 Go to file From c9e81f0cc630cea052574ce7c50b3e82145bb626 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Use THT electrolytics, finish SMT layout, try on quentin font for size From d8deca9307af08e321f2f6168a97d7f0d7734956 Mon Sep 17 00:00:00 2001 Subject: [PATCH] A couple more GND-stitch vias From 77735c00cc3285131373f5cfc61b82eab5963d12 Mon Sep 17 00:00:00 2001 Subject: [PATCH] rm project libraries Hardware/PCB/precadsr/fp-lib-table | 1 | Conn_01x02.
- Vertex -5.59382 4.18518 7.89166 facet.
- 7.200788 H 2.3346394 2.1692854,7.0433077.
- 6.113461e+000 9.983999e+000 vertex 5.678241e+000 1.176720e-002 1.747200e+001.
- 9.864330e-001 -1.641642e-001 0.000000e+000 vertex -5.642653e+000.
- Mode 100644 .gitmodules delete mode 100644 Schematics/Enlarge/Enlarge.kicad_pcb create.