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FFC/FPC, 200528-0210, 21 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py Nexperia wafer level chip-size package; 15 bumps (6-3-6), 2.37x1.17mm, 15 Ball, 6x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32u575og.pdf#page=306 ST WLCSP-100, ST die ID 467, 3.09x3.15mm, 52 Ball, X-staggered 7x5 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l4p5ve.pdf ST WLCSP-115, ST die ID 495, 4.4x4.38mm, 100 Ball, 10x10 Layout, 0.55mm Pitch, https://www.dialog-semiconductor.com/sites/default/files/da1469x_datasheet_3v1.pdf#page=740 VFBGA-100, 10x10, 7x7mm package, pitch 0.8mm; see section 7.6 of http://www.st.com/resource/en/datasheet/DM00257211.pdf WLCSP-49, 7x7 raster, 3.89x3.74mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f446ze.pdf WLCSP-81, 9x9 raster, 3.639x3.971mm package, pitch 0.65mm; see section 6.3 of http://www.st.com/resource/en/datasheet/stm32f103tb.pdf LFBGA-144, 12x12 raster, 7x7mm package, pitch 0.4mm; see section 6.1 of http://www.st.com/resource/en/datasheet/stm32f103ze.pdf Lattice caBGA-381 footprint for ECP5 FPGAs, 27.0x27.0mm, 756 Ball, 32x32 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=25 FBGA-78, 10.5x9.0mm, 78 Ball, 9x13 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=26 ST uTFBGA-36, 0.25mm pad, 3.6x3.6mm, 36 Ball, 6x6 Layout, 0.5mm Pitch, https://www.ti.com/lit/ds/symlink/dac80508.pdf Analog LFCSP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/4001f.pdf), generated with kicad-footprint-generator connector JST ZE side entry Molex Mini-Universal MATE-N-LOK, old mpn/engineering number: 1-770621-x, 6 Pins per row.

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