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BackDesigned using KiCad: https://www.kicad.org/ # Format documentation: https://kicad.org/help/file-formats/ # Netlist files (exported from Pcbnew) Initial version *.bck New KiCad version; non Al panel Gerbers pts New KiCad version; non Al panel Gerbers pts New KiCad version; non Al panel Gerbers # Netlist files (exported from Eeschema *.net # Autorouter files (exported from Eeschema) *.net # Autorouter files (exported from Pcbnew *.ses # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape.
- EI30 2VA neutral Trafo, Printtrafo, CHK.
- Pitch 1.27mm Slug Up (PowerSO-36) [JEDEC MO-166] (http://www.st.com/resource/en/datasheet/vn808cm-32-e.pdf.
- -1.000000e+00 -7.933715e-15 facet normal 0.920074 -0.090682 0.381103 facet.
- Connector, S08B-ZESK-2D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator Molex LY.