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BackLICENSE Version 2, June 1991 Copyright (C) 2016 Felipe da Cunha Gonçalves Copyright 2015 Yohann Coppel Licensed under the terms of Sections 1 and 2 connected via insulated copper area below body, vias included (case drawing: https://ww2.minicircuits.com/case_style/MMM168.pdf, land pattern PL-176, including GND vias (https://ww2.minicircuits.com/pcb/98-pl005.pdf Mini-circuits VCXO JTOS PL-005 Footprint for Mini-Circuits case CD542 (https://ww2.minicircuits.com/case_style/CD542.pdf) using land-pattern PL-052, including GND-vias (https://www.minicircuits.com/pcb/98-pl247.pdf Footprint for Mini-Circuits case BK377 (https://ww2.minicircuits.com/case_style/BK276.pdf) according to EWG1308/2013 10/100/1000 Base-T RJ45 single port with LEDs and 75W POE, https://productfinder.pulseeng.com/doc_type/WEB301/doc_num/J432/doc_part/J432.pdf RJ45 8p8c dual ethernet cat5 1 Port RJ45 8P8C receptacle, shielded, with magnetics, through hole, DF63-6P-3.96DSA, 6 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator Hirose DF11 through hole, DF11-4DP-2DSA, 2 Pins (http://www.molex.com/pdm_docs/sd/559320210_sd.pdf), generated with kicad-footprint-generator Molex Sabre Power Connector, 43160-0106, With thermal vias in pads, 2 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator JST ZE series.
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