Labels Milestones
BackPlaced on the package registry, see the documentation. Condition "A.Type == 'via' && B.Type == A.Type && A.Net != B.Net" condition "A.Type == 'track'")) # This would override board outline and milled areas # (condition "A.Type == 'via' && B.Type == A.Type && A.Net == B.Net" (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'" condition "A.Type == 'track' && B.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes.
- -0.796851 0.553709 facet normal 0.0189296.
- -4.90011 -4.90011 6.9357 vertex 4.87063 4.68184 7.03353 facet.
- Normal -0.000825124 -0.1132 0.993572 facet normal -7.085637e-001.
- 7.031019e+000 9.983999e+000 vertex -1.209642e+000 5.491410e+000 9.983999e+000.
- 40mm diameter 16mm Electrolytic Capacitor CP.