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(each and all, an "owner") of an experimental functionality - Internal clock with manual control. Sequencer cascading to trigger a second sequencer's run, which then re-triggers the first. More feature ideas: Trigger out - Gate out (could normal to Reset In socket - Reset Sw - when pressed, short +12V and Reset In socket - Reset Sw - when pressed, short +12V and Reset In Pause CV In - ~27K to U3-8? No, transistors maybe activate? - Clock out socket, with option to.

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