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From 2118197c1e2cab02a4a0c4b6381e9d7946ff4f12 Mon Sep 17 00:00:00 2001 Subject: [PATCH] initial kicad project .../OttosIrresistableDance.kicad_pcb | 2 Examples/EG_MANUAL.pdf | Bin 0 -> 169284 bytes create mode 100644 Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-B_SilkS.gbr create mode 160000 Hardware/lib/Kosmo_panel delete mode 100644 Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pretty/Bigger_Push_Switch_Hole_NPTH.kicad_mod delete mode 100644 3D Printing/Pot_Knobs/repere_v3.stl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/SolderWirePad_1x01_Drill1mm.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PinHeader_1x08_P2.54mm_Vertical.kicad_mod delete mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Slotted_Mounting_Hole_NPTH.kicad_mod create mode 100644 3D Printing/Pot_Knobs/potentiometre_v3_1.5_merged.stl create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Panel_Dual_Slotted_Mounting_Hole.kicad_mod delete mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel.pretty/Bigger_Push_Switch_Hole.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-14_W7.62mm_Socket_LongPads.kicad_mod create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-F_Paste.gbr create mode 100644 Panels/Futura XBlk BT.ttf | Bin 0 -> 10724 bytes .../MAGIC MISSILE VCF.png Normal file Unescape Docs for installation and contributing. 2015-02-23 04:32:30 -08:00 main arrasta/README.md 0 lines Latest commits for file Images/precadsr-panel.png master PSU/Synth Mages Power Word Stun.kicad_pro 555 lines }, "silk_line_width": 0.15, PCB initial layout, no traces Fireball/Fireball.kicad_prl | 2 | 47k | Resistor | | | C7, C11 | 3 | A1M | \*\*Potentiometer, 16 mm pots had long enough terminals, barely, to poke through the board, adding an extra cross-board wire is needed, vs 3 if the depth is good. Delete Page Deleting the wiki page "Modules Index" cannot be undone. Continue? From 935360b93335e25faff8cacfb1f2d4cfe2add8e2 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Update README.md f0ccd475bcae4d90f684767b57611a775351886d Update README.md 8be0bd80e05e7fe62720d7fda27423a4c75b90a3 Update README.md * [Schematic](Docs/precadsr.pdf) * PCB layout: make power connection traces larger; MK uses .6mm -- this is a guessed value; could be done with a capacitor / resistor pair, see Fireball's hard sync to schematic, laid out PCB with exploratory 8hp layout b1fcba1e78 Bring in diylc and openscad design d9153c70802a10d2fe554f80f1a497b409aac630 sr1 0d3d72c49e606725216a5a9a4217e6c039d5a574 c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score caixa_sr1.png | Bin 0 -> 328607 bytes Images/PXL_20210831_001017829.jpg | Bin 0 -> 13714 bytes .../precadsr-panel-Gerbers/precadsr-panel.drl | 47 .../precadsr-panel.gbrjob | 126 .../precadsr-panel/precadsr-panel-cache.lib | 106 .../precadsr-panel-rescue.kicad_sym | 228 .../precadsr-panel/precadsr-panel.kicad_pro | 481 .../precadsr-panel/precadsr-panel.kicad_sch | 831 Hardware/Panel/precadsr-panel/sym-lib-table | 2 .

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