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Series, see https://standexelectronics.com/wp-content/uploads/datasheet_reed_relay_DIP.pdf DIL DIP PDIP 2.54mm 22.86mm 900mil 64-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils Toshiba 11-7A9 package, like 6-lead dip package with pin 2 and 13 removed for voltage clearance (UCC256301, https://www.ti.com/lit/ds/symlink/ucc256301.pdf SOIC, 14 Pin (JEDEC MO-153 Var BF https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator Molex.

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