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Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: merged pull request 'new_footprints' (#5) from new_footprints into main ... Footprint "SOCKET_3_PIN_HEADER_NORMAL" (version 20211014) (generator pcbnew main arrasta/arrasta_playbook_v0.9.txt.

4.127373e-001 -7.075863e-001 5.735586e-001 facet normal -0.00473867.
2x21, 2.54mm pitch, 8.51mm socket length, double rows.
Vertex -7.38912 -4.93725 5.07603 facet.
177.6375 76.4625 (end 188.1 112.

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