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Plated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 38764 bytes Panels/futura medium bt.ttf // 13 SPDT switches Subject: [PATCH 02/13] More notes 812d609d12a788e600a582b2b6e7494f6d2b0728

-0.4 3.34543 11.3902 vertex.
Normal -0.365743 -0.30016 0.880986 facet normal -0.271031 0.654318.
200528-0050, 5 Circuits (http://www.jae.com/z-en/pdf_download_exec.cfm?param=SJ038187.pdf), generated with kicad-footprint-generator.

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