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BackPM EDT Generated from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 Merge pull request 'Finish schematic, add PDF' (#2) from schematic into main afea9d5a2c Final revision; added custom DRC as project file Fireball/Fireball.kicad_dru | 102 Fireball/Fireball.kicad_pro | 4 | | | Tayda | A-1847 | | | | | | Q1, Q2, Q3 | 3 | 2N3904 | Small Signal NPN Transistor, TO-92 | | R9 | 1 Kosmo_panel | 1 | 2_pin_Molex_header | 2 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1.
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