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Request 'Fix rail clearance issues, make all power traces large Add ground fills, fix some clearance issues, make all power traces large "rules": { PCB initial layout, no traces Fireball/Fireball.kicad_prl | 2 aoKicad | 1 | B10k | Potentiometer | | | J6, J10, J11 | 3 Hardware/PCB/precadsr/precadsr.sch | 412 Hardware/PCB/precadsr/precadsr.xml | 884 main MK_VCO/Schematics/MK_VCO_RADIO_SHAEK_W_PARTS.diy 6789 lines Latest commits for file Fireball/Fireball.kicad_dru main synth_tools/Schematics/SynthMages.pretty/SLIDE_POT_0547.kicad_mod 84 lines tstamp 189e5c14-d81a-45a9-b8ba-c69582490088) Final revision; added custom DRC as project file tstamp 60305f7c-b08f-48d5-a3e4-4d4a9046f92f) Final revision; added custom DRC as project file attr exclude_from_pos_files exclude_from_bom) Final revision; added custom DRC as project file tstamp 42deceed-4793-4b11-91d8-f336ff75a562) Final revision; added custom DRC as project file tstamp 30cbcf99-eb70-4e15-8409-33e0ecd46602) Final revision; added custom DRC as project file ) (polygon (pts Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file afea9d5a2cf23e2a33a2927086270d4d602f5a2b 46614f2341 Go to file f45c980890 Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane Updates from real TL0x4, fix pots being backwards, tighten up schematic, fit letter instead of latch, https://www.neutrik.com/en/product/nc3fahr-0 A Series, 5 pole male.

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