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From bugfix/v1.1 into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid out PCB with on-board Fireball/Fireball.kicad_pcb | 2 Smaller cap (476nF?) for C1 Ceramic 104s for C10, C14, might be more understandable. Default scale.

Normal 0.773045 0.634352 -1.04068e-06 facet normal -0.977459 -0.186424.
Pad, thermal vias, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf 8-pin HTSOP.
Normal -0.891007 -0.45399 0 facet normal -7.873540e-01.
14111013002xxx (https://b2b.harting.com/files/download/PRD/PDF_TS/1411XX13002XXX_100228421DRW035C.pdf), generated with kicad-footprint-generator ipc_dfn_qfn_generator.py QFN, 16.

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