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Back[eTSSOP] (see Microchip Packaging Specification 00000049BS.pdf VQFN, 16 Pin (https://www.haloelectronics.com/pdf/discrete-ultra-100baset.pdf), generated with kicad-footprint-generator Hirose FH12, FFC/FPC connector, FH12-25S-0.5SH, 25 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py VQFN, 32 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/doc0015.pdf), generated with kicad-footprint-generator Molex MicroClasp Wire-to-Board System, 55935-0810, with PCB trace layout created pull request synth_mages/MK_VCO#5 Add jlc constraints DRC; replace order number text Add jlc constraints DRC; replace order number text 613d1b6f7ef8de710893bbeb40d56c8d26d50247 @circuitlocution.com created pull request synth_mages/MK_VCO#7 Updates from real TL0x4, fix pots being backwards, tighten up schematic, fit letter instead of A4 48790c2294 Fix for two bugs.
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