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BackLTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File 3D Printing/Jigs/eurorack_jig_v2.stl Executable file Unescape Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Mounting_Hole.kicad_mod Normal file View File 3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/BLADE BARRIER.png a924f97182 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 47687 bytes Hardware/PCB/precadsr/precadsr.pro | 258 Hardware/PCB/precadsr/precadsr.xml | 1557 Hardware/PCB/precadsr/sym-lib-table | 3 | A1M | Potentiometer | | L1 | 1 Hardware/lib/aoKicad | 1 | 1uF | Unpolarized capacitor | | | | C4, C5 | 2 | 10uF | Electrolytic capacitor | Tayda | A-2939 | | | D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 | 8 | 1N4148 | 100V 0.15A standard switching diode, DO-35 | | Tayda | A-1157 or A-2425 | | J3 | 1 | Synth_power_2x5 | 2x5 pin shrouded header 2.54 mm spacing 3 pin Molex header 2.54 mm spacing"/>
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- -0.679089 0.485175 vertex -6.43867 0 7.3242 vertex.
- Normal -0.28858 -0.951321 0.108209.
- MK_VCO_RADIO_SHAEK_W_PARTS.diy Executable file View File 3D.