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Back*.ses # Exported BOM files *.xml *.csv # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File https://youtu.be/v9A9n-kMjz0?t=209 (until ~4:30 New: A.
- -0.0992428 -8.20381e-05 0.995063 vertex -0.50268 -7.98986 19.9434.
- 9.923323e-01 vertex -1.060534e+02 9.665134e+01 8.881824e+00.
- Vishay, TJ4, http://www.vishay.com/docs/34079/tj.pdf L_Toroid.
- Normal 0.0546198 -0.55473 0.830236.