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Back2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks merged pull request 'new_footprints' (#5) from new_footprints into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/3 More schematics Schematics/Luthers_Perfboard.pdf | Bin 0 -> 461484 bytes Panels/title_test_36.stl | Bin 0 -> 11692 bytes .../HOLD PORTAL.png | Bin 0 -> 15005 bytes Panels/FireballSpellVertVerySmall.png | Bin 0 -> 146728 bytes Images/IMG_6771.JPG | Bin 0 -> 16369 bytes main synth_tools/Schematics/SynthMages.pretty/Micro SPDT (3 pin).kicad_mod Normal file Unescape Fireball/Fireball.kicad_pro Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/LED_D5.0mm.kicad_mod Normal file View File Panels/FireballSpell_Large.webp Executable file View File 3D Printing/Cases/Eurorack 2-Row/d6aac07ae9184a927e3520e79cd5c366_preview_featured.jpg Executable file View File Images/loop.png Normal file Unescape module label(string, size=4, halign="center", height=thickness+1, font=default_label_font) { color([1,0,0]) linear_extrude(thickness+1) text(string, size, halign=halign, font=font_for_label); } //module title(string, size=9, halign="center", font="Futura XBlk BT:style=Extra Black") { // XKCD (alt tags we don't need to be fixed elsewhere Schematics/Enlarge/Enlarge.kicad_sch | 206 Update README.md Don't put R8 so close to R26 -- D36/R47 too close Testing before powering up: Clock In Normal - 1k to U2-8 (AND NOT short to U2-10 Clock Rate - variable resist +6k between U2-8 and U2-9 Reset Sw - when pressed, short +12V.