synth_tools

Back

0.247369 -0.963815 0.0993414 facet normal 9.972108e-01 5.731455e-03 7.441644e-02 vertex -9.055054e+01 1.008513e+02 1.085210e+01 facet normal -2.537102e-001 4.349550e-001 8.639706e-001 facet normal -0.706045 -0.0555529 0.705985 vertex 4.4 0.747025 18.8084 facet normal -0.0419323 0.554724 0.830977 facet normal -4.01859e-05 -0.0975714 -0.995229 facet normal 0.0635213 0.807211 0.586836 vertex 4.33881 -2.47079 19.9 facet normal 0.156321 -0.0122986 0.98763 vertex 5.14703 0 18.8084 facet normal 2.129188e-001 -3.650230e-001 9.063243e-001 facet normal -0.0497529 0.0861751 -0.995037 vertex 8.75916 -4.81539 0.0445979 vertex 8.91331 -4.48913 0.0389554 facet normal -0.634341 -0.773053 -5.92546e-06 facet normal 4.496485e-001 7.868857e-001 4.226431e-001 vertex -1.600258e+000 -4.947547e+000 2.480400e+001 facet normal -0.257144 -0.137446 0.956549 facet normal -0.0808284 -0.0827209 0.993289 vertex 5.83299 4.3279 7.92316 vertex 5.83003 4.3315 7.92322 vertex 4.28775 5.77664 7.9152 facet normal 4.225759e-001 1.881651e-003 9.063256e-001 vertex -5.161758e+000 9.619175e-001 2.491820e+001 facet normal 0.0815293 -0.0819688 0.993295 vertex -4.10478 -5.1829 7.85113 vertex -4.12613 4.97321 7.83559 facet normal 9.315864e-01 5.164725e-03 3.634833e-01 vertex -1.081544e+02 9.695134e+01 4.656011e+00 facet normal 0.22956 -0.181238 0.956271 facet normal -4.080780e-001 6.992349e-001 5.869777e-001 facet normal 0.766702 0.634275 0.09931 vertex 7.28969 6.84547 0 facet normal -1.600434e-001 2.743748e-001 9.482113e-001 facet normal -0.237813 -0.388084 0.890413 facet normal -0.262695 0.257305 0.929939 vertex -4.89431 -5.50428 6.95641 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf ## Git repository From 40ce306867b3d353457e134a232ee65f5767bece Mon Sep 17 00:00:00 2001 Subject: [PATCH] Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s re-re-remove the mysterious extra trace re-re-remove the mysterious extra trace f33ea6a168 Add scad for v3.2 3afa35e4b1 PCB initial layout, no traces Initial kicad, images, gitignore for kicad backups afea9d5a2c Final revision; added custom DRC as project file tstamp 52a45927-621d-4774-9080-e26ba88e3d95) Final revision; added custom DRC as project file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md file adds README.md file Binary files /dev/null and b/3D Printing/AD&D 1e spell names rendered as raster using Filmoscope Quentin Normal file Unescape Hardware/Panel/precadsr_panel.png Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-B_Cu.gbr Normal file Unescape f33ea6a168 Go to file 6523065365 updates the potentiometer pads and thermal vias; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l152zd.pdf WLCSP-64, 8x8 raster, 5x5mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f429ng.pdf UFBGA-201, 15x15 raster, 13x13mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=263, NSMD pad definition (http://www.ti.com/lit/ds/symlink/lm4990.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf Texas Instruments, DSBGA, 3.0x1.9x0.625mm, 28 ball 7x4 area grid, YZR pad definition Appendix A BGA 225 0.8 CSGA225 Spartan-7 BGA, 15x15 grid, 13x13mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=279, NSMD pad definition Appendix A BGA 1156 1 RF1157 RF1158 Virtex-7 BGA, 42x42 grid, 42.5x42.5mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=265, NSMD pad definition (http://www.ti.com/lit/ds/symlink/opa330.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf Texas Instruments (http://www.ti.com/lit/ds/symlink/tps22993.pdf QFN, 24 Pin (http://www.ti.com/lit/ds/symlink/bq25601.pdf#page=54), generated.

New Pull Request

Labels Milestones