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BackEeschema *.csv *.lck ########################## # Additional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file View File Schematics/SynthMages.pretty/Switch.dcm Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-F_Cu.gbr Normal file View File RadioShaek2Board.diy Executable file View File Schematics/shaek_try_1.diy Normal file View File Hardware/PCB/precadsr_aux_Gerbers/precadsr-NPTH.drl Normal file View File Synth_Manuals/VALMORIFICATION+Build+and+BOM.pdf Normal file.
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