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Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_SilkS.gbr From 8de432ba4663cc4e208cff778a114b9ae41e7906 Mon Sep 17 00:00:00 2001 .../Panels/MIRROR IMAGE.png | Bin 0 -> 15005 bytes Panels/FireballSpellVertVerySmall.png | Bin 0 -> 10724 bytes .../MAGIC MISSILE VCF.png differ v1.1 Go to file f45c980890 Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability Change transistor footprint to inline_wide, fix DRC ground plane created pull request 'new_footprints' (#5) from new_footprints into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file version 1) #Kicad 7 # 2-layer, 1oz copper condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" (condition "A.Net != B.Net" (condition "A.Type == 'via'" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" (condition "A.Type == 'track' && B.Type == 'graphic')" # This would override board outline and milled areas # (condition "A.Type == 'via' && B.Type == A.Type" condition "A.Type == 'via' && B.Type == A.Type" condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == A.Type" (condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'" condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'via' && B.Type == A.Type" (condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" From f12031bb4117bdc0bfa93734f5e1f978a14297b0 Mon Sep 17 00:00:00 2001 Subject: [PATCH 14/18] replaces FIREBALL.

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