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Mechanical' && B.Type == 'track'" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 10:22:31 2021 e6b834b08c Fix floating pin for op amp Add kicad schematic, some diylc noodling 4d47ea2710 Initial stab at a 10-step panel layout 3bfacc0b86 Add main pdf a924f97182 Minor layout tweaks Minor layout tweaks From 8f3ce8359ba460976b5ffcbe5a92590e33120bbc Mon Sep 17 00:00:00 2001 .../Panels/MAGIC MOUTH.png | Bin 0 -> 31384 bytes .../Pot_Knobs/potentiometre_v3_1.5_merged.stl | Bin 0 -> 37432 bytes Panels/Font files/futura light bt.ttf From 303a55e23667987c98f6d6f4be567bff3180e8cb Mon Sep 17 00:00:00 2001 Subject: [PATCH] revised README.md to rev 2 d89db83df1 revised README.md to rev 2 beta by adding +5V, and both trigger/gate and CV routing updates led holes to 5mm + unplated, and revises jack footprint 16c50fa0a8 Add pulldown resistors for reset debounce cap; formatting checkpoint before getting really weird with WireIt dd8c61c34f A couple more minor clearance tweaks 68726f9fe0 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin History e825437e5d Upload files to '3D Printing/AD&D 1e spell names in Filmoscope Quentin/PRISMATIC SPHERE.png differ Binary files /dev/null and b/3D Printing/Pot_Knobs/scaled_french_pot.mix differ Binary files /dev/null and b/Images/IMG_6771.JPG differ Binary files /dev/null and b/Panels/FireballSpellSmall.png differ Binary files /dev/null and b/Docs/precadsr_layout_back.pdf differ Binary files /dev/null and b/Images/IMG_6771.JPG differ Binary files /dev/null and b/Panels/Font files/futura medium bt.ttf differ From 2ce1144628c5b348c6a2166a7b906cc45e80a76d Mon Sep 17 00:00:00 2001 Subject: [PATCH] Finished PCB, passes all passable DRCs Footprint selection, some PCB layout choices Add CV in to pause the clock Add CV in to pause the sequence. Probably can't do, or impractical: CV-controlled clock. Presumably the CV in to pause the clock feature/seq_chaining Checkpoint before trying to implement chaining sandwich Move LED resistors From d81094c64ef3dbd9cdcdc0341bc85fcc9deb080e Mon Sep 17 00:00:00 2001 Subject: [PATCH] added the once through idea with commentary by 496e3e3344 Correcting changed filename in .prl 54f1a61ba5 gets jiggy with PCB locator, 6 Pins per row (https://www.hirose.com/product/en/products/FH12/FH12-24S-0.5SH(55)/), generated with kicad-footprint-generator Diode SMD diode bridge Diotec SO-DIL Slim, see https://diotec.com/tl_files/diotec/files/pdf/datasheets/b40fs.pdf SMD diode bridge OnSemi SDIP-4L, see https://www.onsemi.com/pdf/datasheet/df10s1-d.pdf OnSemi Diode Bridge SDIP-4L SMD diode bridge Vishay KBL rectifier diode bridge Thermal enhanced ultra thin SMD package; 3 leads; body: 4.3x6.1x0.43mm, https://www.vishay.com/docs/95570/to-277asmpc.pdf 3-pin TSOT23 package, http://cds.linear.com/docs/en/packaging/SOT_8_05-08-1637.pdf Texas Instrument DRT-3 1x0.8mm Pitch 0.7mm http://www.ti.com/lit/ds/symlink/tpd2eusb30.pdf DRT-3 1x0.8mm Pitch 0.7mm Texas Instruments, DSBGA, 1.36x1.86mm, 10 bump 3x4 (perimeter) array, NSMD pad definition Appendix A Spartan-7 BGA, 14x14 grid, 8x8mm package, pitch 0.4mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32l476me.pdf WLCSP-81, 9x9 raster, 3.639x3.971mm package.

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