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Wafer level chip-size package; 15 bumps (6-3-6), 2.37x1.17mm, 15 Ball, 6x3 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb55vc.pdf ST WLCSP-100, off-center ball grid, ST die ID 483, 3.73x4.15mm, 115 Ball, Y-staggered 11x21 Layout, 0.35mm Pitch, https://www.st.com/resource/en/datasheet/stm32h7a3ai.pdf ST WLCSP-156, ST die ID 494, 3.3x3.38mm, 49 Ball, 7x7 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32l562ce.pdf ST WLCSP-90, ST die ID 456, 1.94x2.4mm, 20 Ball, 4x5 Layout, 0.4mm Pitch, https://www.ti.com/lit/ml/mxbg419/mxbg419.pdf, https://www.ti.com/lit/ds/symlink/tmp117.pdf Texas Instruments, DSBGA, area grid, NSMD pad definition Appendix A BGA.

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