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BackAdditional ignored # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 0 Minor layout tweaks Finish schematic, add PDF 2d3c489f2a More SR1 notation SR 1.pdf More SR1 notation main master PSU/Synth.
- -0.257144 0.956549 vertex -7.46035 3.09018.
- 0.016946 0.828689 0.559453 facet normal -0.181147 0.338927.
- 9.832457e-01 1.822821e-01 -1.015564e-03 vertex.