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BackIrd*sin(lf0), h1], [ ird*cos(lf2), ird*sin(lf2), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/Panel/precadsr-panel/precadsr-panel.kicad_sch Normal file View File Mon 10 May 2021 12:33:34 AM EDT
- 0.417288 0.880977 vertex -7.69994.
- -4.455212e-001 0.000000e+000 vertex 1.107587e+000.
- AR Path="/607ED812/609384DB" Ref="#FLG03" Part="1" AR Path="/607ED812/6091D1B4.