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Counter expects CLOCK to pass 1/2 of V+ (i.e. 6v) but many external clock sources cycle between 0v and 5v max // gate out (j4/j10 // clock in (j2/j11) // casc out (j14/j15 // reset/casc in (j1/j13) // gate out (j4/j10 // clock out (j5/j12) // glide in (sleeve and normal both GND 6x Sockets, 2pin: - Glide attenuator (B10k) (join two left pins from below Clock rate goes down when resistance goes up, opposite to expectation. C1 is too small for a single.

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