Labels Milestones
Back*.csv *.lck ########################## # Additional ignored # KiCad backups folders temp_* # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes count 0 Minor layout tweaks.
- 0.589577 7.19149 vertex -6.85859 -0.790944.
- -0.693269 -6.94378 7.20613 vertex 6.81829 -0.589577.
- 3-826576-6, 36 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xx-dv-xe-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-thru.pdf), generated.
- -0.0761286 0.995139 facet normal -0.995186.