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BackDocumentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: make power connection traces larger; MK uses a ground plane Change transistor footprint to inline_wide, fix DRC ground.
- 4.10478 7.85113 facet normal 2.908002e-001 2.368463e-003.
- Vias (https://www.infineon.com/cms/en/product/packages/PG-DSO/PG-DSO-12-11/ Infineon SO package 20pin without exposed.