synth_tools

Back

0.0819588 -0.993262 facet normal 9.807886e-01 -1.950737e-01 0.000000e+00 vertex -9.657910e+01 1.060488e+02 1.855000e+01 vertex -9.617960e+01 1.059924e+02 1.855000e+01 vertex -9.500859e+01 9.211231e+01 1.855000e+01 vertex -1.024702e+02 9.381525e+01 1.055000e+01 facet normal -3.267694e-001 -5.718470e-001 7.524711e-001 vertex 1.341195e+000 3.939920e+000 2.488700e+001 facet normal 0.129484 -0.780815 0.611197 vertex -6.81829 -0.589577 7.19149 vertex 4.29047 5.40904 7.37319 vertex 5.40021 4.41978 7.20613 vertex 5.23815 4.40436 7.19149 facet normal -0.0620211 0.0778225 0.995036 vertex 4.28949 -6.75916 19.9463 vertex 5.86835 -7.35868 20.0916 vertex -3.02394 -7.70489 19.9688 facet normal -4.792343e-001 -8.386599e-001 2.588127e-001 vertex 1.630534e+000 4.844471e+000 2.475471e+001 facet normal -0.277896 -0.916106 0.289006 facet normal 0.063536 0.807242 0.586791 vertex 4.01935 2.40334 19.8418 vertex 5.57623 -2.17372 19.9 vertex 4.01273 2.44513 19.9 facet normal 0.6852 -0.343403 0.64232 facet normal -0.82034 0.163178 -0.548101 facet normal 0.471711 -0.881672 -0.0119957 facet normal 0.30016 -0.365743 0.880986 facet normal 0.758301 0.622313 0.19418 vertex 8.47298 5.66146 0 vertex -5.00013 7.48323 3.82299 facet normal 8.884379e-01 4.589969e-01 0.000000e+00 vertex -1.024704e+02 1.039873e+02 2.655000e+01 facet normal 0.096218 0.976244 0.194139 facet normal -9.127763e-01 -4.084597e-01 -3.071142e-04 facet normal 9.127763e-01 4.084597e-01 -2.140456e-04 facet normal -4.566403e-001 7.828531e-001 4.226355e-001 vertex 2.572281e+000 -4.415690e+000 2.480400e+001 facet normal -0.181148 0.3389 0.923218 vertex 3.54289 8.26214 3.82299 facet normal 0.622313 -0.758301 0.19418 facet normal 9.527696e-01 3.036928e-01 8.499575e-04 vertex -1.041733e+02 9.652563e+01 2.655000e+01 facet normal -5.955997e-001 -2.447308e-003 8.032777e-001 vertex 5.170141e+000 -2.984018e+000 2.488918e+001 facet normal -2.880153e-004 -5.040268e-004 -9.999998e-001 ## Documentation: ### Documentation: * [Schematic](Docs/precadsr.pdf) * PCB layout: [front](Docs/precadsr_layout_front.pdf), [back](Docs/precadsr_layout_back.pdf) * [BOM](Docs/precadsr_bom.md) * [Build notes](Docs/build.md ``` git clone git@gitlab.com:rsholmes/precadsr.git git submodule init git submodule update Find and replace last few thin traces, fix teardrops and gnd fill Find and replace last few thin traces, fix teardrops and gnd fill Corrected: Shifted C5 so one of their own. 2015-04-27 02:11:47 -07:00 Binary files /dev/null and b/Schematics/Luthers_VCO_schematic.pdf differ main synth_tools/Schematics/SynthMages.pretty/PinSocket_1x02_P2.54mm_Vertical.kicad_mod 42 lines synth_tools/PCB Notes.txt 17 lines Notes from MK's PCB livestream # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] submodules .gitmodules | 6 From f51b7b97734e404127fa5d5d263acbfd66f116e4 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Initial kicad, images, gitignore for kicad backups From f835c1b52669c83e3b7ee8bb7127766f514de308 Mon Sep 17 00:00:00 2001 .../Panels/FIREBALL VCO.png | Bin 0 -> 163520 bytes Images/IMG_6777.JPG | Bin 77965 -> 0 bytes Binary files /dev/null and b/Datasheets/tl074.pdf differ Binary files /dev/null and b/Panels/Futura XBlk BT.ttf | Bin 0 .

New Pull Request

Labels Milestones