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0d3d72c49e606725216a5a9a4217e6c039d5a574 Mon Sep 17 00:00:00 2001 Subject: [PATCH 04/18] adds front panel Added schmancy pcb for v2 front panel Added schmancy pcb for v2 front panel and pcb into different files Add a front-panel PCB d40f7ca1ca Experimenting with more panel layout ideas out_row_1 = v_margin+12; slider_bottom = v_margin+8; module label(string, size=4, halign="center", font="Futura XBlk BT:style=Extra Black"; // waves out // cv switch // Note: don't mess with them. // this gets added to the extent prohibited by law if you need a hole, set this value to zero. // Diameter of the knob spacing on the Program) on a work based on EPCOS app note at http://www.cypress.com/file/140006/download DFN, 6 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/mic5353.pdf), generated with kicad-footprint-generator JST PUD series connector, B12B-ZESK-D (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator Molex Micro-Fit 3.0 Connector System, 5268-14A, 14 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py SOP, 16 Pin (https://www.analog.com/media/en/technical-documentation/data-sheets/4001f.pdf), generated with kicad-footprint-generator JST PUD series connector, B5P-VH (http://www.jst-mfg.com/product/pdf/eng/eVH.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py mlf 8 2x2 mm 16-Lead Quad Flat, No Lead Package (MD) - 4x4x0.9 mm Body [SOIC] (https://docs.broadcom.com/docs/AV02-0169EN SOIC 1.27 SSO, 7 Pin Double Sided Module Texas Instruments DSBGA BGA YZP R-XBGA-N8 Texas Instruments, DSBGA, area grid, YZF, YZF0016, 2.39x2.39mm, 16 Ball, 4x4 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32mp151a.pdf ST TFBGA-225, 13.0x13.0mm, 225 Ball, 15x15 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=23 FBGA-96, 13.5x7.5mm, 96 Ball, 9x16 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=24 FBGA-78, 10.5x8.0mm, 78 Ball, 9x13 Layout, 0.8mm Pitch, https://www.st.com/resource/en/datasheet/stm32h7b3ri.pdf ST TFBGA-257, 10.0x10.0mm, 257 Ball, 19x19 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stm32mp151a.pdf ST UFBGA-73, 5.0x5.0mm, 73 Ball, 9x9 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g483me.pdf ST WLCSP-81, ST die ID 461, 4.63x4.15mm, 115 Ball, X-staggered 18x10 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g483me.pdf ST WLCSP-81, ST die ID 468, 3.15x3.13mm, 49 Ball, 7x7 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=25 FBGA-78, 10.5x9.0mm, 78 Ball, 9x13 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=28 FBGA-96, 14.0x9.0mm, 96 Ball, 9x16 Layout, 0.8mm Pitch, https://www.infineon.com/cms/en/product/packages/PG-LFBGA/PG-LFBGA-292-11/ LFBGA-100, 10x10 raster, 4.618x4.142mm package, pitch 0.4mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32l072kz.pdf WLCSP-49, 7x7 raster, 3x3mm package, pitch 0.5mm; see section 7.5 of http://www.st.com/resource/en/datasheet/stm32f303zd.pdf WLCSP-100, 10x10 raster, 4.618x4.142mm package, pitch 0.65mm VFBGA-86, 6.0x6.0mm, 86 Ball, 10x10 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g051f8.pdf#page=102 ST WLCSP-25, ST die ID 494, 3.3x3.38mm, 49 Ball, 7x7 Layout, 0.4mm Pitch, YFF0006, NSMD pad definition Appendix A BGA 324 0.8 CS324 CSG324 BGA 324 0.8 GateMate FPGA Maxim WLP-12, W121H2+1, 2.008x1.608mm, 12 Ball, 3x4 Layout, 0.5mm Pitch, https://www.adestotech.com/wp-content/uploads/AT25SL321_112.pdf#page=75 WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.4mm; see section 7.1.

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