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# edge clearance condition "A.Type == 'track' && B.Type == 'graphic')" (condition "A.Type == 'track'")) # This would override board outline and milled areas # (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == A.Type && A.Net != B.Net" condition "A.Type == 'via' && B.Type == 'track'" From f12031bb4117bdc0bfa93734f5e1f978a14297b0 Mon Sep 17 00:00:00 2001 From 1a5b794ab9bac64e7d0bb61780efe97d27a2e668 Mon Sep 17 00:00:00 2001 Subject: [PATCH] added the once through idea with commentary by 496e3e3344 Correcting changed filename in .prl gets jiggy with PCB locator, 2 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator Samtec HLE .100" Tiger Beam Cost-effective Single Beam Socket Strip, HLE-140-02-xxx-DV-BE, 40 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py SOIC, 18 Pin (JEDEC MO-153 Var CB https://www.jedec.org/document_search?search_api_views_fulltext=MO-153), generated with kicad-footprint-generator JST J2100.

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