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BackVertex -9.41467 3.89968 0 facet normal 6.034096e-17 -5.396832e-16 -1.000000e+00 facet normal 3.267669e-001 5.718420e-001 7.524760e-001 facet normal 4.720715e-001 -8.093078e-001 3.495273e-001 facet normal 0.188007 0.291191 0.938009 facet normal 0.768426 0.630721 0.108223 facet normal -1.215679e-14 -1.000000e+00 -4.728938e-15 facet normal 0.976242 0.096139 0.194186 facet normal -6.353877e-001 7.721933e-001 0.000000e+000 vertex 4.575243e+000 -3.392458e+000 9.983999e+000 vertex 5.197721e+000 4.781580e+000 9.983999e+000 vertex -4.519133e+000 -5.470537e+000 1.747200e+001 facet normal -2.429559e-02 -1.331102e-03 9.997039e-01 vertex -1.068524e+02 9.725134e+01 8.826184e+00 vertex -1.066276e+02 9.695134e+01 8.831248e+00 facet normal -9.720735e-01 -2.346750e-01 -9.051373e-04 vertex -1.043264e+02 1.007833e+02 1.608622e+01 facet normal 0.382434 0.0376662 0.923215 vertex -1.78367 8.96712 3.76384 vertex 6.89515 5.7167 3.82299 vertex -8.83147 1.71116 3.82299 facet normal 0.119234 0.101837 0.98763 vertex 5.14703 0 18.8084 vertex 4.16916 -0.710463 18.8084 facet normal -0.0980465 -0.995182 6.66873e-06 facet normal 0.290279 0.956942 -7.53346e-07 facet normal -0.0973802 -0.995182 0.011361 facet normal 0.0694843 0.705398 vertex -9.46879 0 3.54602 facet normal 0.436801 0.865139 0.246453 facet normal 0.0620396 -0.0777953 -0.995037 facet normal 9.996062e-01 2.806048e-02 -0.000000e+00 facet normal 0.0433039 -0.0700998 0.9966 facet normal -8.773147e-01 0.000000e+00 -4.799155e-01 vertex -1.072454e+02 9.725134e+01 5.240735e+00 facet normal -0.772589 -0.634804 0.0114014 facet normal -0.422844 -0.331516 0.843386 facet normal 0.499998 -0.866026 0 facet normal -0.989167 0.0992487 0.108159 facet normal 0.0221491 -0.0970093 0.995037 vertex 7.63518 -2.35514 19.9494 facet normal -1.011997e-14 5.429241e-15 -1.000000e+00 d8eca8dc7e Go to file b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'Fix rail clearance issues, make all power traces large "rules": { PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces Fireball/Fireball.kicad_prl | 2 | 47k | Resistor | | S2 | 1 | ICM7555xP | CMOS General Purpose Timer, 555 compatible, PDIP-8"/>